PLC Scan Cycle

1. What Is a Scan Cycle?

A PLC executes its program repeatedly. One pass is called a scan cycle:

• 1. Read inputs.
• 2. Execute the program.
• 3. Update outputs.
• 4. Repeat.

Understanding this cycle helps explain FBD diagrams, timers, latches, and short signals.

2. A Simplified Cycle

[Inputs] → [PLC program] → [Outputs]
    ↑                         |
    └─────────────────────────┘

The PLC continually returns to the beginning and checks the inputs again.

3. Step 1: Read Inputs

At the beginning of a scan, the PLC reads whether Start or Stop is pressed, a part is detected, a door is closed, a fault is active, and the drive is ready.

The program uses these sampled values during the current scan.

4. Step 2: Execute the Program

In FBD, execution evaluates the connected blocks:

[Start_Button] ──┐
                 ├── [AND] ──> [Motor_Run]
[Safety_OK] ─────┘

If Start_Button and Safety_OK are TRUE, AND produces TRUE for the Motor_Run command.

5. Step 3: Write Outputs

After evaluating the program, the PLC updates its outputs. External devices then receive the new command state.

The simulator displays this as a change in an output block's state.

6. Why the Cycle Repeats

Operators press buttons, sensors switch, and mechanisms reach end positions. The PLC must keep reading inputs and recalculating logic. A changed input is processed at a subsequent scan boundary:

Scan 1: Start_Button = FALSE → Motor_Run = FALSE
Scan 2: Start_Button = TRUE  → Motor_Run = TRUE
Scan 3: Start_Button = TRUE  → Motor_Run = TRUE

7. Example: Button and Lamp

For a direct Button → Lamp connection:

The output changes after the next evaluation of the logic.

8. Short Pulses and Edges

If a program should respond to the moment of pressing rather than a held signal, use an edge detector or a latch.

Button state: FALSE → TRUE → TRUE  → FALSE
Rising edge:  FALSE → TRUE → FALSE → FALSE

An edge is the transition between states, not the duration for which a signal is held.

9. Memory Between Scans

Some blocks retain state across scans. A latch can remember a brief Start command and keep Motor_Run TRUE after the button is released.

Without memory, the output often stays active only while the input is active. With memory, the program can retain the state.

10. Timers and the Scan Cycle

Timers also rely on repeated evaluation: each scan checks the input and elapsed logical time.

For TON, Q becomes TRUE only after IN has remained TRUE for the preset duration.

11. Simulator Practice

Open the lesson example and start the simulation. It combines a counter, timer, and latch through OR into Output 1. Input 1 counts pulses, Input 2 starts TON, Input 3 sets the latch, and Input 4 resets the latch and counter.

Keep the other inputs FALSE while testing one path. Briefly activate Input 3, release it, and observe that Output 1 stays TRUE. Activate Input 4 to clear the latch. Then activate Input 2 and observe the configured 10000 ms timer delay before Output 1 becomes TRUE. Clear Input 2 to reset the timer. Compare this retained or delayed behaviour with the direct connection in the first lesson.

The goal is to see that outputs are recalculated repeatedly, while stateful blocks retain information between scans.

12. Key Points

The PLC repeats input reading, program execution, and output writing. Distinguish a held signal, a short pulse, and a block that remembers state between scans.