Binary Half Adder

1. What Is a Binary Half Adder?

A half adder is a combinational logic circuit that adds two one-bit binary numbers, A and B.

The result is represented by two signals:

• `SUM` — the least significant bit of the result;
• `CARRY` — the carry into the next bit position.

The half-adder expressions are:

SUM = A XOR B
CARRY = A AND B

2. How the Diagram Works

The XOR block produces the sum. Its output is TRUE when the input signals are different.

The AND block produces the carry. Its output is TRUE only when both inputs are TRUE at the same time.

This is combinational logic: the outputs depend only on the current A and B values, and the circuit stores no internal state.

3. Truth Table

The final row demonstrates the key rule of binary addition:

1 + 1 = 10₂

SUM contains the least significant bit, 0, while CARRY contains the most significant bit, 1.

4. Testing the Half Adder in the FBD Simulator

The lesson program sends A and B to both the XOR and AND blocks. XOR writes the SUM output, and AND writes the CARRY output.

1. Open the program in the simulator. 2. Start simulation mode. 3. Set A = FALSE and B = FALSE, then execute a scan. 4. Repeat the check for FALSE/TRUE, TRUE/FALSE, and TRUE/TRUE. 5. Compare SUM and CARRY with the truth table.

These four input combinations provide a compact test of the XOR block, the AND block, and the complete diagram.

5. Why Is It Called a Half Adder?

A half adder adds only two input bits:

A + B

It does not accept a carry from the previous bit position, so it is not sufficient for adding multi-bit numbers.

A full adder includes a third input, `CARRY_IN`, and calculates:

A + B + CARRY_IN

6. Practical Applications

In a typical PLC program, a half adder is rarely assembled manually from XOR and AND blocks because the controller normally supports integer arithmetic. The circuit is still useful for learning and for some bit-level tasks.

Learning Binary Arithmetic

The half adder shows how logic operations form an arithmetic result. It connects Boolean algebra, digital electronics, and controller programming.

Working with Individual Bits

Some programs process individual flags or status-word bits instead of whole numbers. Such tasks may require:

• a result bit;
• a carry flag;
• an indication that two inputs match or differ.

Testing Logic Functions

A half adder is a compact training test for XOR and AND. Four truth-table rows cover every possible behavior.

Specialized Logic

The same combination is useful outside arithmetic:

SUM = A XOR B
CARRY = A AND B

SUM indicates that exactly one of the two signals is active, while CARRY indicates that both are active. For example, when diagnosing two sensors or commands:

• SUM = TRUE — the states are different;
• CARRY = TRUE — both states are active;
• both outputs are FALSE — both states are inactive.

7. Building More Complex Circuits

Full Adder

A full adder can be built from two half adders and one OR block.

First stage:

S1 = A XOR B
C1 = A AND B

Second stage:

SUM = S1 XOR CARRY_IN
C2 = S1 AND CARRY_IN

Final carry:

CARRY_OUT = C1 OR C2

Multi-Bit Adder

Several full adders can be connected in sequence. The carry from each bit position becomes an input to the next:

bit 0 → bit 1 → bit 2 → bit 3

This is how 4-, 8-, 16-, or 32-bit adders are constructed.

Arithmetic Logic Unit

Adders are part of a processor's arithmetic logic unit. Combined with other circuits, they support:

• addition and subtraction;
• incrementing a number;
• address calculation;
• number comparison;
• counter processing.

Counters and Incrementers

Incrementing a binary number also causes carry to propagate through successive bit positions. Adder logic is therefore used when building hardware counters and incrementers.

8. Summary

A binary half adder adds two bits without a carry input. XOR produces the least significant SUM bit, while AND produces the CARRY bit:

SUM = A XOR B
CARRY = A AND B

This simple circuit connects truth tables with binary arithmetic and provides the foundation for full and multi-bit adders.